For Soc Hardware And Software Partitioning Algorithm And Ip Core Design And Realization

With the development of IC technology, the chip's density rises very quickly. A system, whichconsists of microprocessor, coprocessor and some other external chips, could be integrated intoone chip. The chip containing a system is called System-on-Chip (SoC).Both the computer circles and the electronic engineering circles have paid large attention to thetechnology of SoC.There are 3 fields in the research of SoC: Hardware Software co-design, IP core's building andreuse, IC technology in very deep sub-micron. This paper emphasize on Hardware softwarepartitioning and IP core design, which are respectively sub-item of the former two fields. Thetwo questions for study are a little independent and a little interdependent.Hardware software partitioning is one key problem of Hardware Software co-design. Thisproblem is a NP-complete optimization problem. The common algorithms are unable to solve itvery well. Considering all the factors, we choose the Generic Algorithm (GA) to deal with thisproblem. This paper presents a GA-based settlement. The result show that the algorithmdesigned resolves the HW-SW partitioning with good stability and high efficiency. Depending onboth the HW-SW partitioning and the GA's characteristic, annealing algorithm and selecting theelder-individuals in the light of probability are introduced into the GA. No less than what weexpected, those two techniques ensure the algorithm's self-adaptability and the result's globaloptimization. Furthermore, the efficiency is heightened markedly.IP core's design is in the base of SoC. This paper presents three IP cores in detail, which arecharacter LCD controller, Timer/Counter and DMA controller. All those tree IP cores' interfacesare WISHBONE compilable. During the designing process, the synchronization between theLCD and the MPU, and the DMA's test problem are emphasized on.