Design And Implementation Of Lightweight Hash Function Reconfigurable Architecture

With the rapid development of Internet of things technology and its related applications,RFID tags,low-end smart cards,wireless sensor networks and a large number of small devices are gradually integrated into people's social life.With the increasingly close relationship between Internet of things technology and people's daily life,people attach great importance to the security of information transmission.Hash function is one of the commonly used information encryption technologies.Because the related devices of Internet of things technology have several limitations in computing power,memory size and power,these limitations bring challenges to the commonly used hash functions,so lightweight hash functions emerge at the right time.Using reconfigurable technology to design reconfigurable cryptographic processor is a research hotspot in recent years.On the basis of ensuring the security of information encryption,it can not only meet the performance requirements of cryptographic algorithm,but also has high flexibility.Therefore,the design of reconfigurable cryptographic processor for lightweight hash function is of great significance.The specific work contents are as follows:Firstly,this paper estimated the lightweight of the existing hash function and based on the principle of the different design its classification,detailed the advantages and disadvantages of different kinds of lightweight hash function,in-depth analysis of the lightweight hash function iteration structure and the characteristics of the internal structure of processing between different algorithms are similar to each use of the basic computing unit.Secondly,from the perspective of reconfigurable computing,the types of basic arithmetic units in the lightweight hash function are statistically analyzed and their order characteristics are analyzed,which lays a theoretical foundation for the design of reconfigurable processing units and the layout of reconfigurable arithmetic units.Then,the reconfigurability of the basic arithmetic unit is analyzed and the basic arithmetic unit is designed as a reconfigurable arithmetic unit according to the characteristics of the algorithm.Combined with the design characteristics and methods of the reconfigurable computing structure,the lightweight hash function-oriented reconfigurable architecture is designed.The configuration flow and calculation process of controller and computing array in reconfigurable architecture and the selection of internal structure and internetwork of reconfigurable processing unit in reconfigurable computing array framework are introduced in detail.Finally,the algorithm mapping process of lightweight hash function on reconfigurable architecture is described in detail,and the reconfigurable architecture of lightweight hash function is designed and logically integrated based on Verilog HDL hardware description language.Under TSMC 55nm process,the clock frequency of the architecture can reach 467MHz and the area is 2.55mm~2.In this paper,the number of equivalent gates is 1.33MGE,the area efficiency is 39.58Gbps/MGE,and the average utilization rate of reconfigurable computing units is39.9%.Compared with COBRA architecture,Cryptoraptor architecture and Pro DFA architecture,the number of equivalent gates is reduced by 1.44?5.03 times,the area efficiency is increased by 1.52?9.72 times,and the average utilization rate of reconfigurable computing units is increased by 10.2%?15.7%.The results show that the lightweight hash function reconfigurable architecture studied in this paper can not only ensure high flexibility and processing performance,but also meet the requirements of realizing safe and efficient lightweight hash function in resource constrained environment.