Research And Design Of Reconfigurable Array For Multimedia Applications

Modern multimedia process is characterized by high real-timing, large amount of data, and high computational complexity. These require high performance of media processors. Meanwhile, different standards of multimedia process require processors to be more flexible. Reconfigurable processor is a new kind of computing architecture which owns both the high flexibility of GPP and high performance of ASIC. So, it provides a valuable research direction for multimedia processing.Multimedia processing algorithms have a rule that the kernel loops account for most of the execution time of the task. Based on this rule, the paper analyzed the algorithm of multimedia process, such as IDCT transform, the calculation of predicted value and the summation operation, and designed a reconfigurable processing array which loops are easy to be mapped on to accelerate the computing. We designed the whole reconfigurable array system from processing element, interconnect, datapath, address decoder to controller. Also, based on the character of high amount of data and high parallelism of multimedia process, we analyzed the bitwidth requirement of parts of algorithm, and introduced sub-word parallelism technology into the design. The sub-word parallelism array can calculate the higher and lower bits of data at the same time, so that the data processing ability of array is doubled. This paper presents the flow of mapping algorithm to the array, and designed a GUI tool to facilitate the mapping process. Also, the paper describled the detail verification flow of reconfigurable array and mapped some typical algorithm on the array. Through the VLSI implementation, we can get the performance of the reconfigurable array.