The Design Of 700V Power Vdmos

Power MOSFET is a new device developing rather quickly in recent years. Vertical double diffused MOS transistor (VDMOS), as an important member in power MOS’s family, has many advantages, such as high input impedance, fast switching speed, high frequency, low power drives, good frequency characteristics, good thermal stability, etc. It has provided strong support strength for the power electronics field to constantly rapid develop, and widely used in switching power supplies, automotive electronics, solar lighting and other markets.With the continuous expansion of VDMOS applications, low voltage and high voltage of VDMOS products is also increasing. For VDMOS low voltage areas, lower on-resistance and smaller power consumption means stronger market competitiveness. And for high-voltage VDMOS, the higher the breakdown voltage, the more design requirements it needs, higher input costs will increase accordingly, and it’s more difficult to get stronger market competitiveness.Firstly, this article describes the development process of power semiconductor devices and its frequency and voltage application range, and details the development and present status of power VDMOS. Then the 700V power VDMOS design process has been introduced. Based on Sentaurus TCAD simulation platform, a power VDMOS with 700V breakdown voltage,2.4Ω,3.0Ω.3.3Ω. on-resistance and 2-4V threshold voltage has been designed. With some restrictions on the production process, through simulation platform, cell structure has been optimized and the on-resistance has been reduced.The termination structure of this paper is based on a failure one to improve and re-optimized design. First, by means of electrical tests、emission microscopy (EMMI) leakage current location and scanning electron microscope (SEM) morphology analysis, failure analysis to a 700V vertical double-diffused metal oxide semiconductor device was done. By a large number of simulations to study the current density, electric field, electrostatic potential and space charge and other simulation models, field plates (FP) problems that results in shortage of breakdown voltage were further discovered and an effective improvement was presented. Eventually, after optimization, a reliable termination with a 770V breakdown voltage and fairly uniform silicon surface electric field around 2.0 E5V · cm-1 was obtained.Finally, the layout of 700V power VDMOS has been designed. Before layout, the cell area of the chip has been estimated. After the layout is completed, the cell areas of these three chips with different on-resistance have been accurate calculations again. By analyzing the results of the on-resistance of tape-out chips, it has found that the average Ron values fit the layout calculation values more than 96%, which performs the reliability of design ways, simulation parameters and the accuracy of layout design.