Optimized Design Of Low-speed Receiver Circuit For WSN

With rapid development of wireless communication, IC design and fabrication technology, short-range wireless communication is getting more and more popular. It features with simple network, low power consumption, and low cost price. Wireless sensor network (WSN) is one of short-range wireless communication. Traditional wireless communication chips cannot meet the requirement of wireless sensor networks, especially in the control of power consumption and chips’ size. a design of baseband receiver is proposed in the thesis, which is low power consumption and low cost price and can be applied in designing WSN chips.Based on the application of short-range wireless communication, the characteristics and the existing technology of short-range wireless communications are analyzed in the thesis. On this basis, the key modules of baseband receiver were studied. Two modulations, such as FSK. and GFSK, and a variety of modulation rate are supported. Direct phase demodulation were identified through the analysis and comparison of commonly used baseband demodulation scheme. A low-IF architecture was designed for the baseband receiver and comprised of a digital down conversion circuit, phase demodulation circuit and the synchronization circuit. Numerically controlled oscillator based on CORDIC and mixer based on Vedic mathematics were designed for optimization of digital down conversion circuit. And the CORDIC module was made use of by NCO and phase demodulation and the area is greatly reduced. According to the optimization of receiver structure,the performance and the implementation were into account, the design and simulation were achieved.A FPGA verification platform was built to complete FPGA verification and test. The results show that the FSK/GFSK modulation signal can be correctly demodulated in the range of rate, and the error rate was less than 0.1%.