Research And Design Of Energy Efficiency And Multi - Band Reconfigurable Sigma - Delta Analog - To - Digital Converter For 4G - LTE Protocol

With prosperity of Integrated Circuits driven by rapid development of wireless communication, multi-mode wireless transceiver design has been a major concern in mobile devices. As the interface between RF front-end and digital base-band, Analog-to-Digital Converter (ADC) is one of the most important blocks in the whole receiver. This thesis aims at the research and design of low-power, energy-efficient reconfigurable∑△ADC, to satisfy the requirements of4G-LTE protocol with multi-band of5/10/15/20MHz.Firstly the fundamentals of∑△ADCs and architectures of∑△modulators are reviewed, and then comparisons between DT-∑△and CT-∑△modulators are given. Solutions to Excess Loop Delay and the design method of Impulse-Invariant-Transfer for the loop filter are summarized as well, particularly encountered in CT-∑△modulators. In this thesis, an energy-efficient, multi-band architecture-reconfigurable CT-∑△modulator is proposed, by means of both simulation and analysis of behavioral discrepancies in modulators under different topologies. In order to optimize the specification of the circuit design, non-ideal effects of CT-∑△modulators are system-level modeled and simulated along with noise-budget.Furthermore, low-power design techniques and reconfigurable methods are intensively studied in this thesis, focusing on the loop filter, multi-bit quantizer and feedback DAC as well as the decimation filter. To optimize energy efficiency, certain configuration schemes are implemented, including opamp-arrays, tunable bias current and mode-switches, meeting distinct requirements of resolution, bandwidth and power consumption in each mode. Considering low-power design, the loop filter employs multi-stage amplifiers to handle high-speed signal, which improves the linearity of the modulator. An interpolating quantizer compatible with reconfiguration is used to relax the wide-band amplifier design. In feedback DAC, switches controlled by low crossing-point and low-swing signals reduce the glitch of DAC current and optimized dynamic power consumption. Techniques of poly-phase decomposition, CSD-encoding and hardware reusage are utilized in the decimation filter to decrease the power consumption. Besides, high-speed DEM algorithm is explored to improve the linearity of feedback DAC.This chip is implemented in SMIC0.13μm1P8M standard CMOS technology with the core area of1.76-mm2. The measured results show it achieves peak SNR of72.7/66.7/60.4/59.0dB and peak SNDR of72.7/66.1/59.9/58.4dB over5/10/15/20MHz BW with the core power consumption of10.5/19.8/22.4/29.6mW from1.2V supply, and the respective FOM of△∑modulator is optimized to0.23/0.44/0.66/0.77fJ/conv. The low-power, energy-efficient multi-band reconfigurable△∑ADC in this thesis can meet multi-band requirements for4G-LTE application.