Csd-coded Fir Digital Decimation Filter Design And Vlsi Implementation

As high-tech is developing, the ADC which is the analog and digital world's interface has been developing rapid in the direction of low-voltage, low power, high speed, high resolution. TheΣ-△ADC is a kind of high prcision ADC. It through the use of oversamplingΣ-△modulation technique to achieve the high prcision that the traditional Nyquist rate ADC is unable to achieve. So theΣ-△ADC become the main technology to achieve the low-speed, high precision ADC and be widely used in the voice coding, digital audio, ISDN, applications. Therefore, the study for the accuracy of theΣ-△ADC converter research on the great significance.This paper introduces how to design the FIR digital decimation filter which can be used in theΣ-△ADC. And detail how to use CSD coding to optimize the filter area. The paper's main functions include:1. I use the given parameters to determine the filter's structure with the signal processing theory and use the MATLAB to simulate the result;2. I use the verilog code to describe the the filter's hardware circuit and use the modelsim to confirm the code can work well. In the paper, I implement two kinds of filters——normal filter and CSD code filter;3. Integrated the filter with the sinplify. By sinplify simulation results, compare with the general filter structure, the CSD FIR filter in area code to save 12%.