| Current wireless communication systems must meet the combined requirements for high-performance, energy efficiency and flexibility. A multiprocessor ring has previously been proposed and it balances its functionality, for a set of signal processing tasks, between ASIC implementations and the use of general-purpose DSP processors. In this dissertation, we discuss the enhancement of its performance, expanding its reconfigurability and exploiting it in energy-efficient applications. We present several novel approaches, based on the processor-ring, which provide good trade-offs between algorithm flexibility, implementation complexity and energy efficiency.;A hardware/software co-design methodology is shown to efficiently realize a blind beamforming algorithm on the multiprocessor ring in an energy-efficient manner. The maximum-power blind beamforming algorithm consists of the computation of a correlation matrix and its dominant eigenvector, which are realized efficiently in FIR filtering form on the processor-ring. The beamformer chip was fabricated in TSMC 0.25-μm CMOS, and it consumes 38 mW for the eigenvector computation at 90 MHz.;In the reconfigurable computing of various size FFT/IFFTs, it is significant to consider the scalability of the power consumption as well as the power consumption itself. A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture has been built and tested. Multi-level reconfigurability is realized by dynamically allocating computation resources required by specific applications. The processor IC has been fabricated in TSMC 0.25-μm CMOS. It performs 8-point to 4096-point complex FFT/IFFT with a scalability in power consumption.;By introducing compare operations into the processor-ring's ALU with minimal hardware overhead, and exploiting variable word-length ALU datapaths, a more flexible eight-processor system retains a powerful but compact instruction set has been designed and fabricated in TSMC 0.18-μm CMOS. Given the ALU's flexible word-length options, the multiprocessor can be configured for 8-, 16-, 24- and 48-bit applications, hence precision and performance can be traded off in favor of power, or vice-versa. Various DSP applications such as FIR filtering, FFT and reconfigurable Viterbi decoding have been implemented with energy efficiency under various configurations. |
