H.264 Encoder To The Box Filter Module Design And Implementation

H.264/MPEG-4 Part 10 is a standard for video compression, and is currently one of the most commonly used formats for the recording, compression, and distribution of high definition video. The final drafting work on the first version of the standard was completed in May 2003. The standard developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG). It was the product of a partnership effort known as the Joint Video Team (JVT) and is jointly maintained.For a member of the H.26x line of VCEG video coding standards, basic processing unit is macroblock, there are various application for block transform and compress in this standard. But accompanied with lower code rate, quantition becomes roupher, and brings same problem-blocking artifects. The phenominone is after re-construction, the neighboring image block appears un-consecutive by view, looks like the image is divided by many blocks, just like mosaic, degrade the quality significantly.In this paper, base on the H.264 coding algotithm, compares with H.26x and MPEG-X coding standard, a deep research was took by quantative analysis, summarized the H.264 coding algorithm's working process and key techniques. For the influence of block artifect's effect on H.264 coding algorithm, my research proposed 2 solutions:optimize the algorithm, and use de-blocking filter.The 2 solutions have their own advantages and dis-advantages. By comparing them, this paper mainly focuses on the hardware realization of in loop de-blocking filter based on ASIC. The de-blocking solution have 2 feature, those are highly adaptive, and complicated circuitry design. In my research, firstly analized the algorithm of filter algorithm and highly-adaptive feature's physical significance, proposed to swap the filting order, introduct transpose buffer, reduce the circuitry's complexity, and, by system optimizing, reduced self-adaptive's selection, enhanced the efficiency of the de-blocking filter. De-blocking filter project base on the entire project requirements, improve the filtering order, increase transpose temporary buffer to optimize the frequence of on-chip SRAM/RegisterFile read/write to once by a macroblock. Pipeline circuit was used to reduce the latency of filter core. A five stage pipeline filter core was implemented with RTL and compiled by Design Compiler on 0.18um ASIC process. After the synthesis and verification, reports show the hardware circuit meet the standard of H.264 with very high-defined throughput. Processing a macroblock with 208 cycles only, which is well adequate to process full high density vedio.