Research Of The Key Algorithms Of H.264/AVC Encoder And Its VLSI Design

H.264/AVC is the most advanced video coding standard in recent years, which covers awide range of application from low-bits communication to HDTV. It gains the experiences fromthe previous video coding standards and the advanced coding technology. Meantime, it hasdeveloped a lot of new coding methods and strategies. The new changes improve the codingefficiency considerably; but unfortunately increase the computation complexity to a large extent,which means large amount of time and resource occupation for H.264/AVC coding system.Therefore it is necessary to develop efficient fast algorithms, in order to decrease the complexityof the system while keeping necessary performance. Besides, the efficient and feasible VLSIarchitecture for H.264/AVC encoder/decoder chip also becomes the hotspot of ASIC designbecause of the market perspective for H.264/AVC application.This dissertation has conducted the research focusing on the H.264/AVC encoderoptimization and its VLSI architecture design. The contents of our work are organized as follows.The paper has conducted a detailed analysis to the most complex module, motionestimation. According to the newly adopted technologies, the fast algorithm of motion estimationis developed in four aspects:①Proposed a fast block-matching algorithm based on search center prediction and searchearly-termination with adaptive search range for the integer-pixel motion estimation, which canspeed up the procedure of integer-pixel search 15 times faster than full search scheme.②According to the fact that block-matching error surface has unimodal distribution withinfractional-pixel search window, we proposed a polynomial model based fast fractional-pixelsearch algorithm. Only 6 candidate points need to be checked rather than 17 candidate points infractional-pixel full search.③Based on detailed analysis of the correlation between the motion vectors and SADs ofneighboring blocks, we proposed a fast block mode decision approach with joint blockmerging-splitting based on adaptive threshold and fast decision equation, which can achieve 66%computation saving comparing to exhaustive block mode checking.Based on the analysis of statistical characteristics of the distribution of the residualcoefficients after linear prediction of image, we have discussed the criterion for all-zero blocksprediction in detail, and developed the optimal threshold for all-zero blocks decision. The proposed all-zero blocks finding algorithm can efficiently lower the computation load of H.264with almost negligible effect on the image quality.The paper also supplied a feasible and efficient VLSI solution for each primary moduleaccording to the developed algorithm. We have defined architecture of high efficiency for theencoder chip. The efficiency of the architecture is presented in following aspects:①An efficientparallel-pipelining processing architecture with 36 PEs is proposed according to the proposed fastBMA. Combining with flexible RAM accessing rule, the architecture can process CIF imagesequence at 25f/s in real-time under 50 MHz clock frequency (5 ref-frames selected, 16×16,16×8,8×16,8×8 enable, 1/4-pel precision, a search range of [-16,16]).②Efficientlytransform/quantization structure is designed and great improvement for deblocking filter isachieved by using edge-filtering reordering, which enables high data throughput over 170K MB/sat 50MHz for transform/quantization and filtering.All algorithms and solutions proposed here have been simulated or verified via experiments.When this thesis is finished, the system architecture and part of components have accomplished,and there are still many works left to perform a system prototype.