Hardware Design Of Adaptive Deblocking For H.264/AVC

H.264/AVC is the latest generation of the international video encoding standard based on JVT(Joint Video Team), which is formed by VCEG(ITU-T Video Coding Experts Group)and MPEG(ISO/IEC Moving Picture Experts Group). It is now one of the hottest discussed problems in the field of image communication. The new standard of H.264/AVC uses a lot of new tools, which increase the efficiency of encoding to twice as quickly as the MPEG-2 standard, but complexity of its algorithm also increases greatly. And counting the limitations of real time calculating in actual use, it has put forth a huge challenge for the realization of hardware. This paper aims at bringing out a design of hardware, which can be used in the H.264/AVC standard adaptive deblocking filter, and this paper also gives the realization of the design.Algorithm is the soul of deblocking. This paper first briefly introduces the relating standard algorithm. Then, it generalizes and summarizes the algorithm. This paper brings out 12 kinds of deblocking models, which effectively reduces the burden of the bus and increases its performance. This paper uses a new filter order, and fully uses the relativity of blocks. The paper abstracts the calculation of boundary strength as well as improves the calculating process, simplifies the design and brings up the performance. This dissertation divides deblocking calculation into four stages and flow processes it, which increases its performance. Meanwhile, these improvements and abstraction brings more convenience to the realization of hardware.The designing is the body of this paper. This paper brings about its own designing structure on the basis of the already-existing designing. Then, it sets up the basic principles of the designing and divides the modules. According to the improved algorithm and the results of the division of modules, this paper brings out the hardware structure corresponding to each module, and gives the procession of the key technology as well.On the foundation of all that is mentioned above, this design realizes the whole structure by using HDL, and then it carries out the simulation by the bottom-up method. This paper gives the testified results of the module level and the subsystem level and provides a brief explanation.Finally, based on the ASIC flow process, this paper executes the synthesis and routing, and it analyzes the result. Under the 0.18μm technology, when the highest frequency is 125M, the the number of gates is 18K.