Used In Communication Systems Low Power, Reconfigurable Research And Design Of The Dac

Wireless Communication has become the most highlight in Integrated Circuit (IC) research and design these years. As one of the key solution to provide a longer battery life and more operation modes, wireless transmitters used in Software-Defined-Radio (SDR) systems comes into the research focus world widely. This thesis aims at the research and design of Digital-to-Analog Convertor (DAC) targeting at the wireless transmitter applications with standards such as WCDMA, TD-SCDMA and GSM.Firstly basic concepts and architectures of DAC are reviewed and mechanics to reduce the non-linearity of current-steering DAC are introduced. And then, the architecture and reconfigurable methodology are derived utilizing a behavior model built based on the application background.Design and optimization of DAC blocks are discussed in details. This thesis emphasizes on the design of the digital filter, sigma-delta modulator, IDAC and analog reconstruction filter. The conversion frequency, transfer function and the word-length of the modulator can all be digitally programmed to satisfy specifications of considered standards. The method to calculate the current and area of the current-source under a special requirement is proposed completely. And by utilizing the switch control signals with limited voltage, the power and harmonic distortion during switching are depressed. The power dissipation is saved by reducing word-length of IDAC and releasing the requirements on the following analog reconstruction filter, while compensating the in-band attenuation by digital filters. Besides, the bias current of analog reconstruction filter is adjusted to further optimize the power consumption for different operation modes. The experiment results have verified both the system and circuit level design methodology.The device is implemented in SMIC 0.13-um CMOS technology with a core area of 0.72 mm2. It operates from a single 1.2-V power supply and consumes 4.6/4.0/2.5-mA for WCDMA/TD-SCDMA/GSM mode, respectively. The measured SFDR and IMD for WCDMA/TD-SCDMA/GSM are 62.8/60.1/74.6-dB and 60.8/59.3/75.3-dB respectively, which show the DAC meets the requirements of the three standards. The realized D/A converter as IP core has been applied on a monolithic multi-mode wireless telecommunication transceiver.