Digital Front-end Of Software Radio Transceiver Design

As the growing competition of different communication standards and the frequency resource shortage, Software Defined Radio (SDR) has drawn more and more attention. SDR is put forward to compatible with different communication standards by software programming. It is open and compatible. Digital Front End (DFE) arises with SDR. It stands between the Analog to Digital Converters (or Digital to Analog Converters) and Baseband. It converts the data of the two parts, playing a role of bridge. Therefore, the DFE with full function and compatible with various communication standards is a key technology for SDR.Firstly, this paper introduces the transceiver architecture according to the basic idea of SDR. Based on the present research situation of SDR, the DFE architecture is put forward. This paper has proposed a configurable DFE for transceiver controlling and sample rate converting. It works for many communication standards such as WCDMA, TD-SCDMA, GSM, EDGE.Secondly, on the basis of the system architecture above, the functions of DFE for transmitter and the necessity to implement are described. It applies the advanced cascading method for the up-sample rate conversion part cascading half-band filters and CIC filters. The five stages cascading method enables the sample rate converter to be configurable and shared by several different standards. It converts the different standards data with different baseband sample rates to the same Digital to Analog Converter sample rate (26 MHz). At the same time, the transmitter DFE has analyzed and applied two key technologies. One is the controller for the carrier leakage cancellation loop which is under the requirement of the transmitter architecture and achieves 31dB cancellation of the carrier leakage power. The other is the controller for the Power Amplifier of the transmitter, which apply the accurate controlling of the output power spectrum of the Power Amplifier.Thirdly, on the basis of the architecture of the receiver, the functions and the necessity to implement DFE for receiver are described. A configurable and multi-standard compatible down-sample rate converter is implemented, and it realizes the sample rate converting from the same sample rate of Analog to Digital Converter (26MHz) to different baseband sample rates. At the same time, an IQ mismatch compensator and a channel selecting filter are designed to decrease the interference caused by the adjacent channels and the IQ mismatch. The Adjacent Channel Selection (ACS) Filter results in more than 40 dB attenuation for the ACS interference. According to the character of the received signal, a digital voltage amplifier is designed with 0 to 63.75dB range with a step of 0.25 dB.At last, the DFE described in this paper has been taped out in SMIC 0.13μm technology. It is compatible for GSM, EDGE and TD-SCDMA standards. The test results show that the EVM feature for GSM transmitted signal is 1.080 and 1.07% for TD-SCDMA transmitted signal. ACS filter has 40dB attenuation for the ACS interference. The EVM feature for GSM received signal is 3.380, and 2.6% for TD-SCDMA received signal. The Power consumption of DFE is 1.63mW.