Research And Design Of Multi-Mode Digital Front-End For TD-LTE/TD-SCDMA Standards

As the 4G evolution version of TD-SCDMA mobile communication technology,TD-LTE technology has become the mainstream standard of quasi-4G technology with its high data rate,high spectrum utilization.Therefore,the research for TD-LTE RF transceiver is of great significance and has broad market application prospects.As a critical block in TD-LTE RF transceiver,the digital front-end(DFE)also faces new challenges: Firstly,compared with 3G technology,LTE need support 6 kinds of channel bandwidth with maximum 20 MHz and MIMO working mode,these requires RF chip to perform double-level digital signal processing at a higher operating frequency.More requirements will be pose to DFE for low complexity,high flexibility,and power consumption;Secondly,the defects such as process constraints,analog component limitations and layout asymmetry in transceiver lead to unavoidable RF impariments,especially the requirements in LTE transceiver such as stringent specfications and mass production consistency,all need corresponding calibration techniques to overcome.Relying on the sub-topic "TD-LTE terminal RF chip R&D" in the national major special project " New Generation Broadband Wireless Mobile Communication ",starting from the perspective of engineering and practical applications,and targeting TD-LTE transceiver for commercial production,and considering the compatibility to 3G TD-SCDMA protocol,a low-complexity and high-flexibility multi-mode DFE for TD-LTE/TD-SCDMA standards is proposed.And based on the digital signal processing function in DFE,for the main RF impairments,the relative digital calibration techniques with Low complexity and high performance are proposed.The specific research contributions of this work include:1.Based on system design and specification analysis,multi-rate multi-stage decimation filtering technique is proposed in the receiver.Accroding to the design specification of seven kinds of channel bandwidths defined by TD-LTE/TD-SCDMA standard,by reasonably allocating decimation rate of every stage and using simple CIC filter and CIC compensation filter at higher frequency and high-order linear filter with coefficients combination at lower frequency,the amount of computation and design complexity are reduced.Under the premise of guaranteeing performance,the area and power consumption of the dual-channel MIMO receiver's DFE are effectively reduced.According to the receiver's dynamic range,an AGC technique based on digital power estimation is proposed.In the transmitter's digital front-end,twice-upsampling digital anti-imaging filter and digital fine-tuning gain control with 0.125 dB step are designed to effectively decrease the design complexity of the transmitter's analog front-end.2.For the DC offset in zero-IF architecture receiver,a two stages DC offset correction technique is proposed.The first stage corrects the DC offset before the amplifier and ADC,avoiding the nonlinear distortion caused by the amplifier or ADC saturation due to excessive DC offset.The second stage quickly and real-time corrects the DC offset based on the first stage,and solves the problem of real-time DC offset changes due to environment and temperature.3.To overcome IQ imbalance in RX(receiver)and TX(transmitter),an on-chip simpledigital compensation scheme is proposed.A digital post-correction and pre-distortion are inserted into the RX and TX DFE respectively,and combined with a digital compensation parameters detecting circuit located in RX DFE,the negative feedback loops for RX and TX IQ imbalance are constructed successively.By the high pass characteristic of the negative feedback loops,the compensation parameters can be converted to DC components and accurately extracted in calibration mode when chip is power on.The measurement shows that with the proposed compensation,60 dB image suppression is achieved in both RX and TX.This ensures a 2.12% and 2.3% EVM of 64 QAM in RX and TX,respectively,comparing to 4.67% and 5.16% without the compensation.4.To suppress TX carrier leakage,a low-complexity digital compensation techniqueis proposed.The digital pre-compensation for I and Q paths is inserted into TX DFE before DAC,and combined with DC offset measurement and compensation parameters detecting circuit in RX DFE,the negative feedback loops for TX carrier leakage are constructed.With the detected power of carrier leakage in digital domain,and by SAR method,I and Q compensation parameters can be accurately extracted in calibration mode while the transceiver starts up.The measurement shows that with the proposed technique,61 dB carrier leakage suppression is achieved.The proposed multi-mode DFE is designed and taped out in IBM 0.13?m CMOS process.Test results indicate that in the receiver's DFE,ACS reachs to 46 dB to 59.5dB under seven bandwidths,maximumly only 2.9dB SNR deterioration is achieved when loading adjacent channels and blocking interference signal,and gain control capability has 60 dB dynamic range and 1dB step accuracy,AGC accuracy achieves ±0.5dB.The overall noise figure of the receiver is less than 6.5dB,and the QPSK and 64 QAM demodulation EVM at-60 dBm input signal strength are less than 3.72%.With a 1.2V supply voltage,the maximum power consumption is 21.12mW(20MHz channel bandwidth)and the minimum is 2.64mW(1.4MHz channel bandwidth).Combined with AFE,the transmitter's DFE has a 70 dB output power linear control range and ±0.125 dB step accuracy,ACLR margin is greater than 21 dB,and the maximum QPSK and 16 QAM modulation EVM at 0dBm output power are 2.86% and 2.42%,respectively.The maximum power consumption is 3.5mW(20MHz)and the minimum is 0.21mW(1.4MHz).All the performances of the design meet the commercial requirements of a TD-SCDMA/TD-LTE mobile terminal,and the design has been applied to commercial 4G data card products successfully.