Design, The Versatile Serial Communication Interface Based On The Compactpci Bus

Presently, the diversification of airborne electronic equipment interface resulted to the data communications between devices difficult, and greatly reduces the efficiency of detecting and maintenance of devices. To solve this problem, and airborne equipment commonly used for serial interface, the subject developed a multi-function serial communication interface board based on CompactPCI bus. Not only to achieve more efficient data communication between different serial devices, but also can more easily complete the function of the automatic detection of multiple different serial interface devices.The subject has adopted to the design scheme of CompactPCI bus control chip+ FPGA+interface level conversion circuits, to achieve 3 channels RS-232,3 channels RS-422 and 3 channels ARINC-429 serial bus communication interface based on CompactPCI bus. The CompactPCI bus is responsible for data communication between the communication interface board and the host computer, the bus interface control chip has adopted PCI9030, witch is provided by the PLX Corporation. The implementation of UART and ARINC-429 data transceiver protocols used by the programmable logic device FPGA, including data transceiver buffers, data format conversion, processing data transceiver protocol and so on. Level-conversion circuit is used to achieve the serial interface signal level conversion between the LVTTL-level and the interface standard level, the level-conversion circuit design of the RS-232 serial bus interface make use of the level-conversion chip MAX211E, and RS-422 serial bus interface adopt the level-conversion chip MAX3490E; But the ARINC-429 bus interface level-conversion circuit is used to build by amplifiers and comparators, To replace a dedicated chip, thereby reducing development costs.In this subject design, the programmable logic device FPGA is the core of the communication interface board, it is mainly responsible for the logic circuit implementation of various serial bus data transceiver protocols. Each channel has designed two independent transmit and receive FIFO memory as data buffers, in order to coordinate the data transceiver rate matching among the bus. Use of field programmable gate array FPGA device to implement data communication among the interfaces and serial communication protocols, not only beneficial to the change or upgrade of the interface bus data transfer specification, but also greatly reduce development costs of the communication interface board. The development of FPGA has the use of VerilogHDL descriptive language on editing the RTL code of the system logic module, and on the integrated development environment QuartusⅡ6.0 platform has accomplished the design,synthesis and layout of the whole interface system, and resorted simulation tool ModelSim SE6.0 to simulate the logic function modules.Finally, the completed design of communication interface board and the corresponding driver program joint testing results show that:the design of communication interface board has been accurate and reliable data communication, but also realized all the functions and targets of the subject requirements.