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FPGA-based UART Interface Protocol Converter Module Design

Posted on:2015-08-11Degree:MasterType:Thesis
Country:ChinaCandidate:J YangFull Text:PDF
GTID:2298330422491508Subject:Aircraft design
Abstract/Summary:PDF Full Text Request
In recent years, with the rapid development of China’s micro-satellitetechnology, the agencies have achieved in terms of space requirements quicklylaunched an active research and made a series of satellite design ideas based plugand play technology. In order to meet the increasing standardization of spacetechnology and universal needs, aiming at micro and small satellite bus interfacestandard for integrated electronic unified, scalable requirements, design methodUART interface protocol conversion module based on FPGA.Electronic systems for domestic and international satellite bus plug and playelectronic interface standards and other technical analyzes, and FPGAprogrammable device technology were studied, as presented to the CAN interfaceexpansion bus design platform electronic system to determine the FPGA-basedUART interface protocol conversion module design program. The program canquickly implement serial protocol conversion and CAN protocols, such a designmethod to improve the flexibility of the satellite electronics system design andshorten the development cycle of the satellite.For CAN bus protocol, UART serial communication interface protocol analyzes,and thus selected communication protocol standards herein conversion module todetermine the specific function of each module in FPGA-based division to achievethis standard. FPGA chip design methodology based on past papers using Veriloghardware description language state machine programming the FPGA chip functions.In this paper, the integration of CAN protocol controller FPGA IP core were studied,which supports the CAN protocol selection criteria in this article, based on theanalysis of its principles on the control module for the controller design. Because ofthe problem of synchronization between the CAN and UART communicationinterfaces of two papers designed FIFO buffer queue to ensure that no data is lostinformation. UART controller based on traditional principles, this paper presents thedesign method of FPGA chip Universal Asynchronous Receiver Transmitter controlmodule, it needs to have a string and conversion functions, and data transfer with theCAN module.The design of the interface protocol conversion module for the register levelsoftware simulation, in order to verify the design of the control module CAN, UARTReceiver, UART transmitter function, the paper transfer process data were specificinstructions, and send and receive through the test module a message transmissionprotocol conversion module to verify the correctness of data. Finally, build a protocol conversion module test platform, the test systemconsists of a computer, protocol conversion unit, CAN bus and other components,based on the system to complete the pass each CAN interface and UART interfacetest data to verify the physical interface protocol conversion unit function. Finally,based on the transmission performance of the module test results were analyzed,demonstrated the feasibility of the design methods used in the satellite electronicssystems.
Keywords/Search Tags:FPGA, UART interface protocol, CAN bus, Plug and Play
PDF Full Text Request
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