Study And Programming Of Logic Synthesis For Multi-output Function

Electronics develops increasingly fast, and the technology has been used in many areas Obvionsly, chip design and analysis are very important. The on-line logic chipset analysis technology, facing to a function cover, is an advanced analysis methodwithout breaking the chip under test. Logic synthesis is a very important subsystem of the on-line analysis technology, for the quality of the final result depends on it strongty.Till now, time-consuming and space-consuming of the analysis system still limit its capacity and efficiency, especially the limited storage, for which are too heavy to be accepted. So trying to downsize the required space-consuming is more necessary and effective. This paper will try to solve the problem by:1. Use the pretreatment subsystem to downsize the cover and reduce the running time2. Enhance the utilization of resource by using optimize the algorithms and programs.To condense the complexity of time is one important problem:to enhance the adjustability of this system is the other one for the two indicators represent the performance of logic s system. We use the random benchmarks to simulate practical problems. In this way we can assure that the result can be seen is specific.Finally we get a new cover with less redundancy which is the equivalent of the prime one. Using the authoritative data to test this system, the result is well acceptable.