Research On Heuristic Logic Reversible Synthesis Algorithm

The on-line reverse decrypting is an important validation method. It has wide application, fast processing speed and other significant advantages. With the development of integrated circuit manufacturing process and increasing complexity of chip structure, its online reverse analysis of working data sets collected from the on-line reverse decrypting expansion rapidly in scale, resulting in that the traditional logic synthesis algorithm can't meet the requirement of cosmic-scale data processing.Based on analyzing traditional logic synthesis algorithm deeply, this paper emphasizes studying logic reversible synthesis algorithm under the condition of the cosmic-scale working data size combining features of data collecting in the on-line reverse decrypting process. The major research content and development are as follows:1. Contrary to the BOOM algorithm lack of effective stop condition, the paper proposed an assistant rule. Through this adding rule, the improved BOOM algorithm can reduce the number of iterations of the algorithm.2. Combined with the improved BOOM algorithm and EspressoII algorithm, this paper designed the Es-ImpBOOM algorithm which can efficiently handle the large scale of working data sets. In this algorithm, firstly using BOOM algorithm to optimized the initial data set in order to reduce the size of data sets to be processed, and then employ EspressoII algorithm to get the optimal cover.3. For the problem that the decoupled model can not efficiently handle the large number of output variable type of data sets, the paper describes and gives a detailed analysis of FC-Min algorithm which is suitable for solving optimal coverage of large output variable types of data sets. And then in allusion to the problem that the output cost of optimal cover solved by FC-Min algorithm is higher than required, the paper presents an improved algorithm. The improved algorithm can spend less time to reach a greater extent to reduce the output cost.4. Based on the above various algorithms, this paper designs and implements the on-line reversible logic synthesis subsystem combining the pratical demand of on-line decrypting system of the logci indefinite chips to reversible system. The results show that the reverse logic synthesis subsystem can accomplish quickly and accurately optimizing the on-line data set to meet online chip analysis systems.