An Fpga Implemented 24-bit Audio Dac With 1-bit Σ-Δ Modulator

Sigma Delta modulation (SDM) uses the technique of over sampling and noise shaping to achieve high resolution for relatively narrow to medium bandwidth signals. Since in audio applications the bandwidth is only several tens of kHz,ΣADC and DAC have dominated this field.This paper presents the design and FPGA implementation of a 24 bit audio DAC incorporating a set of multiplier free interpolation filters and a 4th order 1 bit SDM. For the fixed point interpolation filters, multiplier free canonical signed digits (CSD) coefficients are chosen to sharply reduce FPGA resources utilization. And the zeros of SDM are psychoacoustically optimized to minimize the total perceived output noise power so that the resultant noise within the signal band becomes unobjectionable to the human ear. Furthermore, in order to eliminate the idle tones notorious in 1 bit SDM, single bit dither of±0.125 amplitude is added while guaranteeing a maximum stable input range of 5.19dBFS.The interpolation filter andΣmodulator are accomplished in digital domain. This feature motivates the author to implement and verify the design in FPGA, which provides a superb prototyping environment and cuts development time. It shows that the whole system achieves a signal to noise ratio (SINAD) as high as 138.4dB with idle tones and noise modulation virtually eliminated, which perfectly meets the requirement of 24 bit resolution.