Research On Circuits Design Method For Error Tolerance

To improve computing system dependability, Error tolerance design technology is adopted as key method. Soft error which is induced by high energy particles is used to be treated as the most important concern in space electrical product design. As the feature sizes of integrated circuits decrease to nm, the critical charge and the working voltage is dropping constantly, and the working frequency is increasing dramatically, even in the ground environment, soft errors induced by neutrons in cosmic radiation andαparticles in packet material pose a great threat to VLSI's normal function. This dissertation aims to the design methods of harden circuits for soft error tolerance. The main research contents and innovations are as follows:Initially, a high reliable radiation hardened by design D-flipflop RHBD-DFF is constructed for single event upset tolerance and single event transient tolerance. This structure has normal function as traditional flip-flop, and could be error tolerant, by the experiments results of SPICE tools, no matter the error happens in combinational part or sequential part in circuits, making sure the value of output is correct.Evaluation on pipeline circuits is done, which have a large number of sequential elements. Based on the high speed requirement of pipeline circuits, the special structure RHBD-DFF which is aiming at single event upset is used. Analysis and comparison are done between entirely harden method and selectively harden method.Finally, based on the results of BFIT tool, flip-flops in ISCAS series circuits are hardened. This hardening method only aims at sequential elements, but can protect whole circuits, including combinational parts and sequential parts. Considering overhead restrictions, this method can use less overhead to obtain more error-tolerance by selectively hardening critical elements.