Hybrid Channel Modeling And New Reed-solomon Soft-decision Decoder Design

The Reed-Solomon code has been widely used because of its excellent ability to correct burst errors and random errors since it is constructed in 1960.According to the way of processing the received signal level,the RS decoding algorithm can be classified into two types which are hard-decision decoding(HDD)and algebraic soft-decision(ASD)decoding.HDD directly quantifies the received level into two levels: 0 or 1,so it is the simplest decoding algorithm.Compared with HDD,ASD algorithms make full use of the channel soft information and can get a better decoding performance.It is widely used in RS digital systems and has become the focus of this field.In recent years,the rapid develop of 5G and other digital communication technologies make higher demands on error control coding which mainly include the requirements for more accurate channel modeling,the requirements for burst error correction algorithms and the requirements for smaller hardware consumption etc.However,there are still some shortcomings in the existing research results above.In this paper,the ASD algorithms and decoder design are studied.Firstly,the burst error channel with long continuous error bits is digitized and the channel noise ratio is computed to identify the channel.Secondly,under the new channel model,the existing decoding algorithm is improved.Based on the burst error detection algorithm and the original RCMA algorithm,the novel burst-detection RCMA(BD-RCMA)is proposed.It can not only provide the reliable information but also give the location of the burst errors.The BD-RCMA algorithm is applied in the fusion error correction algorithm BCHDD-LCC.Finally,the hardware design is realized and synthesized under Synopsys Design Compiler.In this paper,MATLAB simulation software is applied to simulate the decoding environment and algorithm.The relevant parameters are determined and optimized by the results of the simulation experiments to improve the decoding performance.The hardware design has been modeled with Verilog HDL and synthesized under Synopsys Design Compiler.It can be seen from the simulation data that the decoding performance of the decoder in the new hybrid channel is better than that of the traditional single channel decoder,which provides a more solid theoretical basis for the application of RS code in the real environment.