Design And Implementation Of A Transformation Model For Software Tasks To Hardware Tasks In Hybrid Cpu/fpga System

With the development of reconfigurable computing technology, embedded systems are experiencing a shift from tranditional micro-controller-based system architecture to the hardware/software hybrid system architecture. In a complex embedded application, as the reason of improving the holistic processing capability and taking the advantage of the hardware tasks, the tasks that require high flexibility are implemented in software, and computation-intensive tasks are implemented as hardware tasks that can execute on FPGAs. Hardware/Software hybrid systems enable system designers to exploit the potential parallism of an application, which can meet the increasing demands on system performance.But hardware/software hybrid systems pose great challenges to system design methodology:such systems require system designers to have experience in both high-level languages and hardware description languages, while most system designers are excellent in only one of them, which greatly impares deisgn efficiency. Based on this stuation, we designed a software-to-hardware transformation tool HTTM, which can transform C codes into the corresponding VHDL codes without affecting the semantics of the program. With this tool, system designers can design the system only in the high-level language level, which reduces system design complexity and improves design efficiency. HTTM takes C programs as its input, and first transforms them into extended FSM representations, which are further translated into the extended BIF language files. According to a set of rules, he BIF files are finally compiled into VHDL language files, which can be fed to the ISE integrated development environment to do simulation and synthesis. Experiment results show that HTTM realizes our design goal, and the generated VHDL files are validated for functional correctness. Conclusions and further work are presented in the last section.