The Optimation Design Two Level Cache Controller On YHFT-DX Chip

Digital Signal Processors have been developmented fast and application widely after being invented. The organization of on-chip memory system affects DSP's performance affect directly.Memory hierarchy structure reduce effectively access penanlty by CPU.In memory system of DSP processor,"Cache+RAM"hierarchy structure is used widely.The two level memory on-chip(L2) is important module for changing data between CPU and DMA.L2's time penalty have large proportion in memory access.It is critical to L2 for improving memory system performance,Desiging the two level memory on chip of hign performance is of great significance.YHFT-DX is a DSP with high frequency and performance in our project. The CPU's frequency get 600MHz in 0.13um COMS's technical.With the 1MB two level memory(L2), it is"Cache+RAM"architecture. So not only may the size of cache configure flexible, also it's expansibility better.This chip of technical path is optimization a original chip,which frequency is 350MHz at the same craft as YHFT-DX.Via reserching deep the original design,This thesis make optimization design on two level cache controller.That frequency get 600MHz,and improving efficiency of dealing with miss request,reducing the power for the two level cache controller.The main jobs and contribution have as follows:1. The two level cache miss pipeline deal with the single miss request have lack,so design the two level cache prefetch architecture as"Stream Buffer",If hits buffer ,L1 can get date ahead two CPU clock cycles.The probability sequential send miss request about 0.14 percent in the L1 of YHFT-DX.Simulaneity the data path may transact parallel,imporving the utilization of bus resource.This amelioration ,which improve the efficiency of L2 dealing with L1's miss request, is approximately 6 percent, which have greatly increase for cache system performance.2. To compromise the power consumption become larger for the high frequency,designing the Tag line prefetch architecture as"Filter"in the two level cache controller.However the Filter buffers were fewer,which lead to the miss probability higher.To make up the defect using Tag way prediction,In level of architecture the single path hit Filter or tag way predict exactly,The L2's Tag in resting state,So the power consumption of L2 reduce by 5 percent than read the fourth way Tag simultaneous.3. To analyse the critical path of the original design, finding the two level cache is the most criticalest of module.In the thesis , several methods were used,such as interface protocol optimized, equilibrium missing pipe line of assignment, the key signal put ahead and hiberarchy reasonable and so on. And custom design was used for the tidy module in the critical path, also timing module for 9 to 512 of encoder seted. Finally, goal of 600MHz attained after the two level cache was come ture by timing optimization design.4. To verification the function of the two level cache controller,used the large test programme in the full chip verification,, for example,the MP4 decoder programme as"Xvid",which complied with CCS, as Benchmark.This article also introduction the flow of RTL logic simulation and the method of accurate fix on bug position.5. To put forward advanced methods about making use of compress L2 line size and partition vertical Bnak to optimize capability and power of the L2's Banks,and evaluating its feasibility.