Mixed Cache Design Optimization

The importance of the memory hierarchy has increased with the process_memory performance gap that computer architects must try to close. When designing an embedded processor, we must pay more attention to choose the architecture, parameters and optimizing technology for the cache so that we can implement an effective memory hierarchy with low hardware cost.This dissertation discusses the design, implementation and optimizing of Cache.The research work mainly includes:1. Analysizing the evaluation measures of memory hierarchy, Setting down the design rule and optimizing goal of the Cache.2. Based on system simulation and timing analysis, choosing the architecture and parameters of the Cache.3. Developing and implementing the optimizing of the unified Cache.4. Validating the design on the FPGA module. Checking all the function check-point.5. Synthesizing the design on SMIC 0.18μm CMOS library by Design Compiler. Optimizing the code for the slack of critical path. The delay of critical path is 9.85 ns.