The Research And The Implementation Of The Generic FFT Processor Based On FPGA

As the science and technology growing on, the theory and technology of digital signal processing has been widely used in many fileds of production and living. FFT (Fast Fourier Transform) which is the most basic algorithm of digital signal processing theory is widely used in the fileds of radar, sonar, communications, geological exploration, image processing, biomedical and so on. The rapid development of technology in these fileds puts forward the higher requirement of the computing speed of the FFT so that many traditional methods to implement FFT can not meet the demand of high speed. Therefore, how to realize the FFT in a more high-speed way is becoming the research content to a number of scholars at home and abroad.As the FPGA (Field Programmable Gate Array) has many advantages such as lower cost, flexibility, short design cycle, high reliability and little risk and so on , it is making FPGA use widely in the fields of communications, image processing and many other fields recent years. Also because of its parallel computing internally, it is making FPGA to do some work of digital signal processing instead of DSP devices in more and more occasions. Particularly when the FPGA used to realize FFT, it can always get a satisfactory result. So FPGA is selected to realize FFT in this design.The 16X16-bits signed number parallel multiplier is completed with radix-4 Booth encoding algorithm and Wallace tree algorithm in the design. The pre-simulation and the post- simulation of the multiplier is done by Modelsim. The multiplier can be realized in the Cyclone EP1C6Q240C8 at the speed of 80MHz. The parallel multiplier is used to design the radix-2 butterfly unit of the core design of the FFT algorithm, and the parallel-serial conversion module, serial-parallel conversion module, shift select module, overflow detection module, address and control module and other modules are designed. The radix-2 FFT module is formd based on these modules and the internal dual-port RAM and ROM of FPGA. The whole module uses the way of time-domain-based extraction, the order of input, output reverse. The pre-simulation and the post- simulation of the design is done by Modelsim. The code used to differ the simulation result from the FFT function in Matlab is created in Matlab and the simulation result is proved to be correct. Finally the design can be able to run at 60MHz in the Cyclone EP1C6Q240C8 stably. The FFT module can realize 1024 points, 16-bit fixed-point complex FFT at about 183us, and it can meet the general engineering requirements. This method can also be used to achieve a lower point or higher points FFT.