Research On 32 Bit High-Speed Floating-Point Multiplier Design

High performance multiplier is the important component of the digital signal processor,the key to implement the signal processing and image processing; Multiplier always has large area, long latency and complex structure. It becomes attractive how to design a fast, simple and regular multiplier. In the past ten years, researchers have developed new Booth algorithm to improve the performance of the multiplier; developed many formal compress trees to make the structure of the multiplier more regular; implement the circuits using pass-transistor logic, multiplexer, dynamic method and so on; the topology of multiplier, which related with physical implementation closely, also developed very rapidly. However, the desire for high performance computation makes the design of multiplier not come to the end.Based on the work in designing a floating-point multiplier in the 32 bit floating point DSP, this dissertation gives a systematic research on the every stages of the multiplier considering delay, area and complex. Based on the study of Booth algorithm, multiplier topology, and the final adder, this thesis introduces and compares kinds of multipliers, implemented a 32 bit high performance parallel multiplier, the exponent and mantissa of which compute in parallel way, modified Booth algorithm and (4:2) compress tree are used to generate and calculate the partial products, carry select adder sums the final two partial products; character vectors and random vectors are used to test the multiplier, the DSP IP includes this multiplier has passed the software/hardware test, and a new multiplier based on this one has been used in the other DSP.The floating point multiplier synthesis with SMIC 0.18um technique, the result show the high performance of the multiplier, under the 1.8V typical condition, the critical path of the multiplier is 4.05ns.