Deep Submicron Cmos Device Gate Oxide Tddb Behavior (tddb) And Its Mechanism

Based on the Percolation theory and defects creation mechanisms of both E model and 1/ E model,a unified percolation model for gate oxide breakdown is brought forward.The trigging mechanism of gate oxide breakdown is believed to be the extending of the localized states induced by the defects such as oxygen vacancy in an oxide.The defect creation dynamics such as oxygen vacancy is described synthetically.As a result,the results of this model both in a high electric field and in a low electric field fit well with the experimental data.So,the long2existing dispute between 1/E and E models is settled.The breakdown characterist ics of ultra th in gate oxide aremeasured under the constant vo ltage and constant current st resses.The reliability characterizat ion methods of TDDB are invest igated.Themeasured results show that charge to break down QBD depends on no t only the quality of the gate oxides but also the st ressed vo ltage,current density and area of gate oxide.A n analyt ical exp ression of QBD is deduced after ext ract ing the fit ted relat ive coefficients.The ext rapo lat ing results according to the described above relat ion are in good agreement w ith the experiment value.A new characterizat ion method of th in gate dielectric TDDB is p resented.This paper presents an experimental method for measuring the density of trapping charges.This method is based on the dynamic equilibrium equation for the process of trapped charges.We can obtain the density and the location of trapping charges by measuring the high frequency C2V curve of MOS capacitance before and after stress,and the change of gate voltage under constant cunent stress.The analytical expression of the density of trapping charges is proposed.The method and the results of parameters extraction are also presented.Experimental results show that this method is convenient and precise.The gate oxide thickness,(tox),of Complementary Metal Oxide Semiconductor (CMOS)processes has been steadily been thinning as a result of technology trends.To keep theswitching power dissipation of integrated circuits at bay,successive technology generationshave relied on reducing the supply voltage.In order to maintain performance, and control short channel effects,however,a reduction in the transistor oxide thickness is required to provide sufficient current drive at the reduced supply voltages.At the 70nm technology node,CMOS processes will have oxide thicknesses of 1.2nm to 1.6nm[1]. Since electric fields in the gate oxide are expected to rise with scaling,the long-term reliability of thin oxides becomes an important concern in modern,deep-submicron(＜0.10μm) processes.In this paper the causes,symptoms,and failure models of gateoxide breakdown will be presented.Section 2 provides some relevant background.Section 3 experiment of gate-oxidebreakdown and what are its causes.Section 4 new model of gateoxidebreakdown in both transistors and circuits.In Section 5 is a summary...