Study And Implementation Of High Performance DSP Fast Mode I~2 C Controller

Recently, with the development of the application requirement, more and more DSP extends I~2C bus on chip so as to communicate directly between DSP and various I~2C peripherals. It is to be one of the key technologies that using limited resource on chip for DSP to communicate flexibly with various I~2C peripherals.This thesis emphasizes on standard cell and full custom design methodology of I~2C controller with various transmission. The proposed I~2C controller with various transmission on the 32 bits floating point high performance YHFT-DSP is designed at specification level, algorithm level and logic level, and is implemented in 0.13μm CMOS process. Furthermore, the verification, emulation and testing techniques of the I~2C which has been applied in an audio system are discussed. This subject mainly contributes to the following aspects:1. An extended I~2C bus specification is proposed. According to the extended specification, an overall function architecture of I~2C controller is designed and optimized. The optimized architecture combines the system-level functional requirements of the independent YHFT-DSP with fast-mode I~2C bus specification.2. The RTL level logical function is designed based on standard cell. The open drain IOBUF and the filter cell are both implemented by full custom design. After deeply studying interface timing constraints on the logical design of the I~2C, it is a strategy to output delayed SDA singnal. An algorithm composed by two steps clockdown is proposed. The two steps are"prescaler"and pulse duration ratio. The algorithm solves the problem how to divide high speed system clock on chip down to produce serial clock of any pulse duration ratio. Main control state machines are simplified to achieve various transmissions with lower hardware cost.3. Both auto-verification and FPGA emulation platform are built to fulfill function and timing verification. YHFT-I~2C successfully communicated with E2PROM on the emulation platform of the DSP. Moreover, the board testing of a sample chip of YHFT-DSP which is applied in the audio system is carried into execution.The testing and application of the sample chip results show the proposed I~2C achieves the basic and extended functions of the specification. Each timing parameter of the designed I~2C could meet the constraints of the extended specification and left margin. The transmission speed can be more than 400Kbps in tipical case. The designed I~2C controller can communicate with several I~2C peripherals correctly. It accomplishes the function of the extended serial bus on DSP and achieves the design goal.