Dynamic Reconfigureable Array Coprocessor Design

This paper describes an improved reconfigurable array coprocessor—IRAC. Compared to other reconfigurable processor designs in the same area, IRAC has improvments in system configuration flexibility and data transfer efficiency. Besides, in IRAC the connection of processing elements is optimized according to the butterfly algorithm in image processing. The simulation results show that IRAC achieves higher performance than most of the other designs in this area.The research work of this thesis includes:The significant difference between IRAC and other reconfigurable processor is that in IRAC the computation array is divided into four quadrant region, during computing the processing elements in each quadrant could do different operation at the same time.Two channels DMA controller is used in IRAC, the data and configure information could be transferred at the same time, which improves the transfer capability of the system.Optimize the interconnection of the IRAC based on the classic butterfly algorithms such as FFT and DCT.The control interface module shields the various differences of the main processor, which improves the portability of the coprocessor system.