SIMD Arithmetic Unit Design Optimization And Implementation With FMA Support

SIMD (single instruction multiple data) is an important way to improvedata-parallel processing capability. With the development of VLSI. Mainmicroprocessor vendors continue to improve the function of the SIMD and vector length.While there are still many bottlenecks like address unalign, data reorganization andcontrol flow.This dissertation have designed a SIMD unit which support fuse-multiple-add(FMA) in high-performance microprocessor, this dissertation optimized analysed andimplemented the SIMD unit base on the applications of scientific computing. Thisdissertation also synthesized and verificated SIMD unit.The main research work and achievements:1. This dissertation implemented a4-way SIMD unit, each way is a7stage FMApipeline. The dissertation propose the configurable hardware support toefficiently execute the overheads which is address unaligned, datareorganization and control flow.2. Verification showed that SIMD floating-point operation meet IEEE754-2008standard, all SIMD function is right. Synthesis results showed that thefrequency of SIMD unit up to2GHz. The area of SIMD unit augmented withconfigurable hardware is2.04%more than the SIMD unit without configurablehardware. The power consumption of SIMD unit augmented with configurablehardware is0.46%more than the SIMD unit without configurable hardware.3. This dissertation analyzed the performance of SIMD unit augmented withconfigurable hardware in DAXPY(Double A Multiple X Plus Y) and sparsematrix application. The results showed that the speedup of configurablehardware is various between1.17~1.50.