Design And Implementation Of The64-bit Integer Arithmetic Unit And Vector Reduction Network On X-DSP

The digital signal processor is an embedded processor for digital signal processing,which is the key of the digital signal processing techniques. Today, DSP is widely usedin the high-end field of communication, multimedia, aerospace and radar. Therequirement of DSP’s performance is increasing, so developing high performance DSPis significant.X-DSP is a high-frequency, high-performance64-bit DSP, which is designedindependently by us. It uses the VLIW Architecture, Harvard bus structure, and itsfrequency is1.5GHz. The64-bit Integer Arithmetic Unit and Vector Reduction Unit(VRDC) of X-DSP is implemented in this thesis, and the Integer Arithmetic Unitincludes Integer Arithmetic Logic Unit and Integer Division Unit.1. This thesis analyzes IALU’s requirement during the design of IALU and designsits instructions. We propose a new type of SIMD64/2*32bits adder structure, which is amixed structure made up with sparse tree adder and carry-select adder. Then using thenew adder with operand isolation low-power technology, we finish the design andimplementation of IALU.2. Based on the Radix-2RNS division algorithm, we put forward the Radix-16RNS division algorithm, and use half custom design method to accomplish the64-bitinteger divider. The core of the RNS algorithm is the data in the form of redundant.Because of the full adder’s carry chain is broken, timing delay won’t be affected by thewide. When calculating a64-bit intermediate data, there is a big advantage on the speed.The divider of this thesis is implemented using a simple structure with less resource,good stability, and it does integer division operation very quickly.3. In this thesis, we elaborate the significance of reduction operation using matrixmultiplication as example, and respectively analyze the execution cycle numbers ofsoftware implementation and hardware implementation. The result of the comparisonshows that the hardware implementation has evident accelerating effect. Based on theVRDC’s designing requirement, we design its instructions. The realization of the wholeunit is divided into three modules, and they are reduction tree module, control module,computing module.4. This thesis studies the verification methods and strategies that used in the designof integrated circuits currently, and on the basis of the study, we carry out the detailedfunction verification on related unit at module level, unit level, SPE/VPE levelrespectively. In synthesis part, we describe the synthesis strategy briefly, list thesynthesis results of each unit and analyze of the critical path. Timing of IALU andVRDC are in accordance with X-DSP’s design requirements, but the divider is still inthe optimization phase of research. The realization of this thesis has laid a solid foundation for the next step to meet the timing requirements.