Architecture Design Of Reconfigurable Computing System For Video Processing

Reconfigurable computing can achive high performance as hardware, while maintaining flexibility as software, so it has a broad application prospect in the video processing area. It has been the hotspot of research and also facing many problems. One is absence of methodology guide when doing the system design. Another is lacking the support of real application performance evaluation.This thesis designs an architecture of reconfigurable computing system for video processing area and describes the design flow, implementation and the verification method in detail.This paper proposes the design flow first. The flow includes the division and extraction of algorithms, software-hardware partition of target application, analysis and information extraction of algorithms and the design of system. According to the flow, the system design is accomplished with H.264 decoder as the target application. This paper elaborates the design process, the system structure model, memory, interconnection, PE components, controller and so on.The algorithms of H.264 decoder are mapped into the specified system. The mapping performance of each algorithm is obtained. The whole system is then modeled on the platform of SoC Designer. With the help of the model, I-ICT of a 16×16 image is accomplished within 390 cycles. In order to get the real performance, the array is implemented in RTL level and synthesized. The front-end synthesis of array using SMIC 180nm process shows that the frequency can achive as high as 300MHz.Taking mapping result, simulation of the whole system and the synthesis performance of the array part into consideration, this paper makes a proper evaluation of the system performance which indicates that without optimization, the system not only supports H.264 protocol bus also satisfies the real-time decoder of formats below SVGA, including 4CIF which meets the task. In the end, the way to raise the performance is proposed, such as carefully arranged data reuse, better mapping, larger bus bandwidth and so on.