Research On Characteirstics Of Interconnect And Thermal Design Technology For Nanometer Chip

With the development of the microelectronics technology, the feature size of chipkeeps shinking, leading to the continuous increase integration level of IC product. Atpresent, the number of transistors in a monolithic processor is more than billion, and thetrend of miniaturization of chip and high performance have become inevitable. However,large power density always limits the development of IC, as a result more and morethermal problems have to be addressed. Meanwhile, the performance, reliability andlifetime have closely relationship with working temperature of chip, thus the estimationand solution for chip heat dissipation is one of key problems needed to solveimmediately.Along with the process of advanced technology, the number of metal layer hasreached13in nanometer integrated circuit, which makes the thermal dissipation pathbecome longer between the low temperature substrate and interconnect in the outmostlayer. Low-k insulating materials have been widly used to obtain better performance.However, these materials also have poor thermal properties which will exacerbate heatproblems. High speed and large drive signal are generally distributed along the topinterconnects to perform good signal integrity. These factors make the most thermal partlocate at the top interconnects. In addition, it is complicated that the estimation oftemperature-dependent Cu resistivity due to various scattering, leading to extremedifficulty for interconnect performance. The presence of thermoelectric coolers maysupply a feasiable solution to alleviate the thermal problems off chip. In view of heatdissipation, this dissertation reveals a systemic investigation of temperature distributionfor interconnect, Cu resistivity modeling and performance optimization ofthermoelectric coolers. The main studies and conclusive results are as follows.1. With consideration of via effect and heat fringing effect, a thermoelectricsimulation method is proposed which modified node heat flow due to temperaturedistribution for top interconnect. Based on the thermoelectric duality, multilevelinterconnects temperature distribution is modeled and simulated with the modified nodeheat flow. The effect of dielectric material and via thermal resistance on temperaturerises is obtained, as well as temperature rise for global interconnects in differenttechnology nodes. Compared with the findings of finite element, the simulation resultsare analyzed with different insulator in100nm technology node. The proposed methodcan be used to make an accurate estimation and can provide a reliable means to forecastor optimize global interconnects in future.2. Based on the drawbacks of tranditional resistivity scattering model, taking into account the surface scattering and grain size effects, an analytical resistivity model ispresented for Cu films. An expression between grain size and metal film is given bycombining the available model with experiment data. The findings show that the grainsize is not equal to the thickness of Cu film, thus the proposed model with considerationof grain size effects is in good agreement with experimental results, which involvesshort computation time. The relative standard deviation of the proposed method can bereduced apparently compared with other models expecially in the range of urtra-thin Cufilm. The proposed model would not only prisicely estimate resistivity for metallic thinfilm but also guaratee the accruracy of latency, power and reliability in integratedcircuits.3. Due to the the limits of circuit performance estimation in conventional EDAtools, we seek to solve it with the help of neural network. Based on BP neural networkmodel, a feedback neural network optimized method is presented for the electricalresistivity of Cu in nanometric dimensions. The number of neurons in hidden layers isoptimized by means of Monte Carlo analysis method. With numbers of trained randomset and test samples, a resistivity prediction model is established by the developedmethod. The findings indicate that a good nonlinear mapping can be obtained betweenelectrical parameters and resistivity of Cu film. Maximum error between availablemodel and the proposed model is less than4%and the outside trained results are in agood accordance with the test samples, which verify precision and generalizationcapability of this method. And it can provide a practical reference for the resistivityperformance estimation with ultra-thin metal interconnect.4. Thermoelectric coolers (TECs) provide an available thermal solution for the heatdissipation problems in current nanometer integrated circuit. In this study, a simplifiedpower model including circuit devices power and repeater power of interconnect lines isderived to address the thermal runaway issue. Based on the surface temperaturedifference and heat-flow density, an equivalent thermal resistance model for poweredthermoelectric coolers is proposed. According to one-dimensional (1-D) thermal model,the steady-state temperature of system is calculated for the same chip with two differentpackage forms. Optimizations of p-n couples are performed with the purpose ofobtaining maximum coefficient of performance (COP) and minimum TECs power.Compared to the traditional flip-flop C4package, the results demonstrate great potentialdecrease of the chip stability temperature and the current optimization can be obtainedwith part of TECs power consumption in50nm technology node. And the analysisresult provides the relationship between the optimizations of COP and power dissipation and electrical current across by TECs.5. The effect of nonuniform temperature distribution in substrate on semiconductormeterial of thermoelectric coolers cannot be neglected. In this paper, a steady-statenumerical model is derived for thermoelectric coolers (TECs) with parameterscontrolled by two-dimensional thermal profiles. Using the thermoelectric duality, wepropose an improved electrical model with temperature-dependent parameterdistribution in the presence of multi-couple pellets. Both electrical element and thermalbehavior are simulated based on this improved model with TEC parameters modifiedaccording to the nonuniform temperature effects. The results demonstrate an excellentagreement with numerical calculation and the proposed electrical model, whichdemonstrates its effectiveness and further improves the estimation accuracy of TEC heatdissipation ability.The temperature distribution approach for nanometer interconnect, metal resistivitymodeling and performance optimization of thermoelectric coolers with temperaturecharacteristic proposed in this dissertation provide crucial solution for earlyperformance estimation and thermal deisgn in integrated circuit.