Cost-effective interconnect and circuit design methods for high-speed nanometer CMOS VLSI design

The semiconductor industry has been following Moore's law over the past five decades because of the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density, lower energy per transition, and better design performance. On the other hand, many new design problems have been introduced due to scaling, and these problems become more significant when migrating from one technology node to a newer one with smaller feature size.;Interconnect scaling is a major design problem in nanometer technologies. Interconnect scaling suffers from increased wire resistance and cross-coupling capacitance to adjacent wires in scaled technologies, both of which lead to significant delay degradation and delay uncertainty. Moreover, chip size has remained roughly constant and the number of components integrated on one chip that require global interconnections is increasing with scaling. These issues made on-chip interconnects, especially global interconnects, a major bottleneck for the performance of VLSI systems. The repeater insertion solution is becoming a problem itself due to the huge number of repeaters in nanometer technologies. Also, interconnects are major contributors to the overall system power, cost, and reliability. This dissertation presents four new design methods for global on-chip interconnects. The proposed methods show significant improvement over conventional design methods.;Designing high-speed and low-power logic circuits with CMOS also faces many challenges because of nanometer technologies. This dissertation presents two new CMOS circuit styles. One style, called SP-Domino, is suitable for wide fan-in logic, and the other style, called Feedback-Switch Logic (FSL), is suitable for general high-speed and low-power circuits. The proposed circuits are compared to their counterparts' static and dynamic circuits and are shown to provide superior performance and power characteristics.;Power consumption and power density are other critical scaling problems. Besides dynamic power, leakage power is becoming very large in nanometer technologies due to the increased integration density and reduced dimensions and threshold voltage of CMOS devices. Power gating is a common method to deal with the leakage problem but introduces latency, power, and reliability overheads during mode transition. This dissertation presents a technique to significantly reduce power gating wakeup overheads while maintaining the low leakage characteristics of power gating. This dissertation ends with some conclusions and possible future extensions.