The Research,Implementation And Chip-level Interface Extension Of Multicore Synchronization Unit

Along with the development of the application requirement and the chip manufacturing technology, single-chip can integrate many more processors and memory resource. The system-on-chip has developed from the single-core to multi-cores. Although this kind of architecture brings huge improvement to the processor performance, it is facing new challenges about synchronization related design, so as to make full use of the processing potential.X-DSP is a brand new high performance multi-core DSP chip developed by the National University of Defense Technology. It is mainly used in signal and image processing domains, which needs a large amount of data processing. X-DSP contains many DSP cores, a global cache and the PCIE module for inter-chip communication. Synchronization mechanism needed to ensure the correctness and efficiency of parallel processing in X-DSP. This paper proposed a distributed synchronization unit in X-DSP. Moreover, a PCIE-NI Bridge is developed to extend the inter-chip synchronization interface. The main work and contribution of this paper can be concluded in the following aspects.(1) We analyzed the hardware and software synchronization mechanism,and proposed the hardware synchronization mechanism based on lock and barrier. This mechanism improved the efficiency of synchronization by reduce the influence to memory access.(2) We designed a distributed synchronization unit structure with hardware lock and barriers. The hardware lock has spin lock and queue spin lock operating modes to reduce the number of lock acquirement request. The hardware barrier adopts broadcast release scheme to reduce hotspot issues caused by traditional serial release.(3) We designed and realized PCIE-NI Bridge, which implements the protocol transformation between AXI, PBUS, DBI, interface and our home-made NI interface. This Bridge facilitates the inter-chip synchronization and data communication.(4) Based on the hierarchical verification method, we complete the module level verification. Then, we finished the system verification at the full-chip level environment, and carried out a joint test for hardware synchronization unit and PCIE-NI Bridge. The logic synthesis result proved that our design satisfied the performance requirement.