Research And Implementation Of The Data Parallel Coprocessor Memory System

Data Parallel Coprocessor DPC, which is scalable and has the powerful data processing ability, is designed for the high performance DSP application market. This thesis addresses itself to the designing and implementation of the multi-level memory system of DPC, including the register files, instruction cache, data cache and the on-chip memory, which is called Scratch-Pad SRAM. In the first part, this paper discusses the key problems in designing architecture of each component, which include why we choose partitioned regiater files, use 2- way connected data cache with write-back strategy and add Scratch-Pad SRAM to original momory system, and how to identify their parameters. Following that, a memory configuration based on the discussion above is presented. In the second part, this paper does deeply research on how to use the memory system effectively. Firstly, this paper proposes a modified register allocation via graph coloring to alleviate port conflicts. And then, it gives some useful approaches of program transformation to reduce Cache conflicts, and concludes three accessing modes in multi-media applications to prepare for the further study of stream cache prefetching technologies. This paper also introduces a data allocation approach to Scratch-Pad SRAM, with the purpose of improving Cache hit rate. In the last part, some core test bench of DSP applications are implemented on the DPC with our multi-level memory system and on the C64 platform respectively. Their execution cycles are compared with each other. And the results show that the DPC has prior advantages to the C64 DSP, which, indirectly but effectively, prove that our memory system works very well.