The Research And Design Of High-speed RS Code In Tactical Data Link Based On FPGA

Reed-Solomon (RS) error-correcting code is the most effective and most widely used one of the error-correcting codes. It is mainly used on digital signal transmission and storage. As the digital signal in the transmission process, there may be subject to a variety of interference and transmission characteristics of the impact of non-ideal signal makes errors, which makes people receive the wrong messages. In recent years, high-speed stability and reliability of digital systems has become increasingly demanding, so error-correcting code in digital signal transmission and storage in the increasingly act as an important role. Research on error-correcting code from the last century, the beginning of the 50's until now, RS error-correcting code is a mobile communication system, deep space communications, digital satellite TV, magnetic recording systems commonly used codes, error-correcting code on the study of RS has important practical significance. How to improve error correction encoding and decoding speed and capacity are particularly important.RS code is a special kind of linear block codes, and its coding technology after decades of development has been more mature. RS code has the use of certain ASIC and application to achieve, given the high cost of ASIC design, as well as poor flexibility, the paper design FPGA-based realization of RS [204,188] codes. And consider the RS code used in Tactical Data Link transmission. Applies as a result of tactical data link communications in the military armed forces, and therefore transfer rate, high signal reliability requirements. In this paper, the use of a reasonable algorithm, select the appropriate error correction code length, as well as the capacity of t, in order to apply to tactical data links to improve the speed, the purpose of reducing error rate.Tactical Data Link has its own Features, such as real-time, reliability, security and so on. Real-time data is transmission to increase the rate and shorten the range the target information update cycle time, reliability data that is reliable and true. In this paper, the tactical data link in accordance with the characteristics of the design of fast long RS code of the codec to achieve and enhance the amount of information data.The first chapter of the thesis the application of RS codes background and tactical data link. Chapters II and III introduces the theory of error-correcting code encoding and decoding, which involve a relatively large number of algebraic theories, these theories are based on RS codes achieve the necessary knowledge, here are a brief introduction. Decoding RS codes is rather complicated, the fourth chapter is dedicated to the interpretation of RS decoding methods, and by comparing the choice of a fast decoding algorithm. The fifth chapter is devoted to FPGA design flow and FPGA realization of the RS codec. Chapter VI completes simulation and verification.