IC Design Of High-speed PLL In DVI Interface Based On SMIC 0.13um Process

This paper introduces the overall structure and constituent parts of the PLL at first. Then, the operation principle of every constituent part has been analyzed, and the basic equation of PLL has been researched. On the basis of getting the basic equation of PLL, a linearzed processing to the circuit has been done. Then, the performance of PLL in noisy environment has been analyzed. Based on the theoretical analysis, the PLL circuit has been divided to be five parts to design, such as phase-frequency-detector, charge-pump, low-pass-filter, voltage-controlled-oscill -ator and divider. After circuit design, pre-layout simulation and post-layout simul -ation have been done by hspice of Synopsys Inc. in SMIC 0.13um process condition. After tape-out and package, the chip has been tested by oscillograph TDS6804B which is made by Tektronix Inc., with the DVI compliance test software version 1.3 inside. The test results indicate that this PLL circuit meets the design requirement.