Verification Of Buffer Administer Module Based On VMM

Nowadays, with the growing of the size and complexity in the chip design, the data show that half to two-thirds of the SoC project failed in the first stream of films. The presence of dysfunction is one of the main reasons. Functional verification has become a bottleneck in the development of digital chips.This paper puts forward a method of building Buffer Administer module's verification platform, which is based on VMM (Verification Methodology Manual), using SystemVerilog language. The hierarchical verification platform which is based on the reusability is mainly studies, and then the function and the achieving method of each one in the verification components are introduced importantly. The new control methods of some verification components are described carefully, and then the reusability of verification component and platform is analyzed. Finally, the testing process of the entire verification environment and the implementation of some test cases are narrated. The statistical results in the three kinds of coverage and simulation waveforms of the designing code in the BA module have been given. In the results, the line coverage is 100%, the condition coverage is 98.66%, and the FSM jumping coverage is 100%. All of the results reached the export conditions of unit testing.