The Design And Implementation Of The AES Cryptographic Algorithm Hardware Accelerator

The security of information has become more important with the development of the information industry. Information security mainly consists of security protocols and cryptographic algorithm. Cryptographic algorithm is the basis and key technology of the information security. These days, the implementation of cryptographic algorithm has the trend to use hardware more than software. The hardware-based cryptographic products have become more and more.The new American data encryption standard AES(Advanced Encryption Standard) has become the international standard in reality. AES is open to the public and free of charge. AES algorithm has good performance in both encryption and decryption and it can be implemented simply, so it is widely used in the information security. Because using hardware to implement the AES has higher encryption speed and better performance, the research on designing hardware of AES algorithm is important. This paper has concerned with the data safe storage and safe transfer, these application situations usually need for high speed, small size and low power. Based on the design technology of Integrated Circuit, this paper has presented a design and implementation of the AES cryptographic algorithm hardware accelerator.First, the finite field mathematical theory has been talked about. Then the entire algorithm flow has been presented, including encryption flow, decryption flow and key expansion flow. Based on this, the hardware implementation has been done. The overall structure has been planned into three parts, including input/output, encryption/decryption and key expansion. To support the several working modes, the basic structure has been selected as the encryption/decryption round transform structure. The S-Box substitution, shiftrows, mixcolumns modules have been designed. The modules are described with Verilog HDL. The encryption/decryption function has been considered together in the implementation of the modules, so it can share the hardware resource and reduce the size of the whole module.