Design And Implementation Of High Performance Encryption/decryption System Based On Fpga

With the development of computer technology, financial transaction processing is experiencing a shift to all electronic systems, and data security is of paramount importance in financial network communication. Currently comprehensive centralized processing systems prevail, and the main architecture is an integration of the bank data host, the composite pre-processing machine and various bank terminal equipments for data and control information exchange. Compared to software implementation, hardware implemented encryption systems are less vulnerable to attacks, and can provide much higher performance to meet real-time requirements, thus dominate financial transaction processing systems.Traditional hardware implementation adopts ASICs, which have problems of low extensibility and high design cost. FPGAs have excellence in reconfigurability, performance and integration density. AS an FPGA-implemented encryption/decryption system can provide better extensibility and higher versatility without sacrificing performance. A FPGA-based high performance encryption/decryption system is designed in this thesis, which implements-8 independent encryption/decryption units for parallel data processing. The data I/O subsystem adopts multi-level Shuffle-Exchange networks to resolve data conflicts due to reuse of the communication channels. Chaotic encryption algorithms are used in our system for higher security for its acyclic, continuous band, noise-like and long-term unpredictable properties.Related background knowledge on chaotic algorithms, Shuffle-Exchange networks and FPGA technology are first presented. The complete system architecture is presented and suitable chaotic algorithms are selected according to the specific application background of this thesis. Detailed implementation is then given, which includes hardware implementation of chaotic algorithms and Shuffle-Exchange networks, pipeline timing control logic, constructure of other hardware modules, system control logic and network communication. A validation platform is also designed for testing of system functionality and performance, and system testing is performed using this platform. The thesis is concluded finally with an outlook of future improvements on our system.