The Verification Technologies And Application In Large Scale Digital IC

As the increasing of chip size, how to verify the whole chip's function in limited time becomes the bottleneck for products which should be put into market as soon as possible. Some data shows that verification takes more than 70% in the whole chip implementation cycle. Thus, how to improve the verification efficiency and reduce the workload of verification engineers is a pressing question.The verification technology in large scale digital integrated circuit can be categorized as follows: dynamic simulation, hardware verification, static verification and physical verification. How to use various verification technologies properly to improve the verification efficiency is very significant to chip implementation. This paper analyzed the verification techniques which include: TLM verification methodology based on dynamic simulation such as AVM, OVM and VMM as well as SVA (System Verification Assertion); FPGA hardware verification; static verification for netlist coming out from synthesis or P&R and the physical verification.The paper mainly researched the TLM verification methodology and proposed an efficient verification structure based on dynamic software simulation and implemented this verification structure in EPA chip verification; considering the complex working environment of real chip, the FPGA hardware verification has been absorbed to ensure the function before tape-out and the point-to-point testing shows that the maximum deviation is only 510ns; the static verification technologies have been researched which include STA and formality. The Primetime and Formality tools were used to verify the netlists coming from synthesis and P&R to guarantee the static timing of EPA and its functional consistency; this paper also analyzed the physical effects which may make chip failure during physical design, researched the reason and proposed the methods to avoid such effects; Some P&R rules have been presented for EPA chip which include clock routing rule standalone setting, considering STA and routing critical path first as well as how to eliminate the antenna effect. Finally, the DRC and LVS has been done to guarantee the chip's sign-off quality...