Simulation And FPGA Implementation Of Channel Encoder And Decoder In Data Link System

As the core technique of the current military information technology, data link technology has shown great strategic and tactical significance and thus it has become one of the research focuses of many countries. With the rapid developments in relative technologies and the deepening of information and electronic warfares, data link technology will play a more and more important role in future wars.Based on the Link-16 tactical data link system, the thesis focuses on the study of error correction coding and decoding techniques of the system. In the first place, the key techniques of the tactical data link system and its basic model are presented in brief. According to the foundation of error correction coding and the specific characteristics of the tactical data link system, the concatenated CRC and RS channel coding scheme is proposed for the data link. Secondly, the tactical data link system employing the proposed concatenated coding scheme is simulated and its performance is analyzed, on the basis of which, the system is implemented through VHDL and functional simulations are performed for the verification of the effectiveness of proposed the coding scheme.The main work of the thesis involves two parts. The first part focuses on the modeling and simulation analysis of data link system base on MATLAB. Firstly, the combined CRC, RS and interleaving scheme is proposed based on the data link standard. Utilizing the proposed concatenated coding scheme, the system performance under various channel conditions is analyzed. Simulation results indicate that through encoding and decoding, the system performance has been greatly improved. The second part mainly concentrates on the FPGA implementation and the verification of the tactical data link system. An interface for the CRC and RS concatenated coding blocks is designed and the key sub-blocks are optimized in accordance with the data structure requirements. In the implementation of the key equations of the RS decoding scheme, the MEA iterative structure is adopted to improve the speed and reduce the resource consumption. Synthesis results show that the requirements on coding and decoding speed are satisfied.