Research On Encoding And Decoding Algorithms And FPGA Implementation Of 5G

Channel coding has received extensive attention as a key technology of the fifth generation communication system(5G).As a coding method that can reach Shannon's limit,polar code have also been extensively studied by people.And finally determined as the coding scheme of the control channel in the 5Ge MBB scene.Since the proposition of polar code,most of the research has focused on the theoretical level,and few research on the realization level.It is of great significance for the application of polar code to study efficient encoding and decoding implementation schemes.In this thesis,based on the study of the polar code encoding and decoding algorithm,the hardware design and implementation of the FPGA-based polar code encoding and decoding algorithm are completed.The main research work is as follows:This thesis first studies the encoding annd decoding algorithm in the polar code.On the basis of understanding the polarization theory,the polarization phenomenon is analyzed in the coding aspect.It also expounds four commonly used methods for estimating the reliability of polarized channels and summarizes the encoding workflow.In terms of decoding,a variety of decoding algorithms for polar code are simulated and compared,including SC,SCL,BP,and CA-SCL decoding algorithms.Through comprehensive comparison,the CA-SCL decoding algorithm is finally determined as the decoding algorithm scheme of this thesis.Another research focus on this thesis is the realization of polar code encoding and decoding algorithm based on FPGA.This part is discussed from two functional modules of encoder and decoder.First,for the encoder implementation part,the thesis introduces the design schemes in detail from the whole to the sub-modules,and explains the interfaces and functions of the modules.Finally,the function of the encoder was verified by the simulation platform combining MATLAB and Modelsim.Secondly,the decoder implementation part was studied using the same design idea,and the timing flow of key modules was explained.Finally,through the ISE software,the encoder and decoder was analyzed for static timing and hardware resource consumption.In the entire FPGA design,cross-clock processing and resource sharing technologies are used,so that the overall design has better timing and reasonable hardware resource consumption.