Research And Implementation Of RS Encoding And Decoding Algorithm In Data Link Symtem

The Link-16tactical data link use a wireless network communication and applicationprotocols, so the reliability of communication is affected by complex electromagneticenvironment on the battlefield. The complex electromagnetic environment on the interferenceto signal is divided into hostile jamming, noise, multi-path interference and multi-userinterference. Therefore, the data link not only use frequency hopping, spread spectrum andtime hopping techniques to improve their anti-jamming capability, but also adopt RS code.Reed-Solomon code is named by its two inventors-Reed and Solomon. It is one kind ofmulti-ary BCH code which has very strong error correction ability. RS code, which is atypical algebraic geometry code, can correct random errors, burst errors and the combinationof both.Besides military communication,it’s widely used in deep space communication,celluarcommunication and DVB system.Also with the improvement of RS arithmetic and thedevelopment of the hardware,the practical application of RS coding will getting moreabroadly.This paper introduces RS code’s application in data link systems, elaborates on theconcepts and basic principles of RS encoding/decoding algorithms, then uses C language tobuild a simulation platform for hard-decision decoding algorithm and soft-decision decodingalgorithm. The simulation results show that: soft-decision decoding can make use of theoutput information and get substantial coding gain.But compare to hard-decision decoding,it’s so complex as to be infeasible in many applications.Through the profound understanding of RS coding, I implement the RS encoding/hard-decision decoding algorithm on Altera’s Cyclone series FPGA with Verilog HDL. TheRS (31,15) hardware decoder base on RIBM algorithm is designed and implemented bypipeline algorithm. To make up the key equation module’s deficient in the whole pipeline, amodified RIBM algorithm is proposed, and the logic resource is also reduced. Besides, theChien search module and the Forney module are assembled and optimized, furthersimplifying the structure of the decoder.Synthesis results show that the maximal frequency ofdecoder is161.21MHz, so the design can meet the requirement of high speed calculation.