The Study And Realization Of Image Procession Based On FPGA

The detection of catenary-pantograph malfunction is extremely significant in current train inspecting. The immense data of the original malfunctioned video image makes simultaneous storaging and transmissioning quite difficult. Because of immensity video images data, it needs advanced video coding and decoding protocol to process. So it can inspect malfunction place simultaneously.As the tenth part of MPEG-4, H.264/AVC has superhigh compress efficiency and excellent internet affinity, it is researched and applied widely. H.264/AVC has advanced algorithm. It has integer transform, quarter-pixel interpolation, multi-mode inter prediction, deblocking filter, entropy coding and so on.This paper uses Verilog HDL to design. With the hardware platform of the Red Cyclone II, it completed the design and the simulative confirmation of the soft core with the hardware descriptive language Verilog in the environment of the exploited tool QUARTUS2 6.0 and MODELSIM_SE6.1B. Based on EP2C35F484FC8 of Altera company's Cyclone II chip FPGA, video capturing, display, some algorithm of H.264/AVC and transmission can be realized.With the outstanding characteristic of flexibility, high speed in design and a large quantity of line resource, FPGA becomes the top choice in various actual applications gradually, combining verilog and VHDL language, it makes great innovation to the design of electric system and make the process faster.In this paper, characteristic of FPGA, flow of design, verilog language were analysed firstly, then static images and video's coding and decoding was analysed in detail, such as transform, quantization, entropy coding and so on; lots of experiments have been done by using H.264/AVC's algorithm based on JM10.2 for different resolution, quantiser parameter, video, and the results of experiment were analysed in detail. Then video images were captured, storaged and displaied based on Red Cyclone II, however, the SAA7113 chip's initializes , the analog to digitial transform of CCD'S signal, inter IC line were analysed. After that, ITU-R BT.601, video synchronization signal's capture were finished. Then video images storage and the control design of VGA display have been done. Finally, some of H.264/AVC's algorithm were achieved using VerilogHDL, after that function imitate has been done and got the result which were predicted before.In this paper, the whole flow of video signal's capture, storage and display have been finished. Parts of H.264/AVC's algorithm has been finished by using VerilogHDL. To some extent, this paper will be beneficial for the video coding and decoding of chip design.