The FPGA Design And Implement Of Trunk Tester

Link transmission equipment is an important part for each communication system. It is located between the switch (or multiplexer) and channel machine to complete the codecing of information. It is needed to test the performance of transmission equipment in the production debugging, testing, inspecting and day-to-day maintenance. However, there is no one tester suitable for a wide range of network, which cause a lot of inconvenience. It is urgent to develop a tester for transmission equipment interface of current network.The Purpose of this dissertation is to build a trunk tester based on FPGA and DSP, in order to help the producing, testing, maintenance and fault location of trunk transmission equipment. There is an active significance for engineering application.The main work of this dissertation is the FPGA design and implementation of tester, including the following:1) A detailed analysis is proposed to the interface types of equipment, the characteristics of the data frame structure. So the structure of tester is designed.2) Signal source of sender according with certain frame structure is realized in FPGA using VHDL hardware description language.3) The designed signal is detected and received synchronously. So the number of error code and delay information of transmission are gained. The information is sent to DSP.