The Design And Implementation Of The Bit Error Rate Tester In Communication Channel Based On FPGA

Bit Error Rate(BER) is very valuable and important to evaluate the performance of communication transmission devices or the quality of a transmission system. And the BER tester is used in the production debugging, testing, inspecting and day-to-day maintenance for transmission equipment, which is used as detection tool for reliability of a communication system.This dissertation comes from a practical research project. The purpose is to design and realize a BER tester in communication channel, which can support many types of networks based on the DSP and FPGA. The BER tester reralizes the following functions based on the structure of traditional BER tester. Firstly, many types of interface of BER tester are suitable for communication systems in order to meet a wide range of network lines testing requirements. Secondly, the output data rate is tunable, nearly from 32kb/s to 8192kb/s. The thirdly, the characteristics of communication channel can be simulated, by inserting manually the delay and the error bit of different distribution characteristics. The fourthly, touch-screen is used for the human-computer interaction, with real-time display intuitively. So users can see the inspection results recorded by FPGA in time.The whole design of the BER tester in communication channel is introducted in this dissertation. The VHDL language is used to realize the functions of signal processing unit on FPGA. The main work includes the following:1,Selecting the types of interface, trunk rates and pseudorandom code as the settings via the touch screen;2,Sending the signal according with certain frame structure;3,Distinguishing synchronous code and detecting bit error rate for the received signal;4,Simulating the characteristics of communication channel by inserting the error bit and delay manually;5,Realizing communication between FPGA and DSP.