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Research Of High Speed Image Pre-processing System Based On FPGA

Posted on:2009-01-24Degree:MasterType:Thesis
Country:ChinaCandidate:Q L KangFull Text:PDF
GTID:2178360278464386Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
With the fast development of modern information age, the information to be processed has been increased rapidly. Image is an important expression of information. The investigations and applications of image processing have draw broad attentions of researchers all over the world. In recent years, the developments of FPGA technology has not only can realize the theoretical achievements in digital signal processing field in practical systems, but also promoted the developments of new theories and applications. The application of FPGA has also play an crucial role in the field of image processing.In this paper, a digital high speed image pre-processing system using FPGA has been designed. The function of this system is to enhance the contrast of the images, remove the noise from the images and detect the edge in the images. This system uses three main algorithms that are Histogram modification and median filter and Sobel edge sharping algorithms to improve the quality of the image. In addition, the dissertation offers improved median filter and improved Sobel techniques which are finally realized in FPGA. All these algorithms work well in the system.FPGA is used as core calculate unit of the image processing system hardware. This part is designed to aim at project application and realized the subject. This system consists of Histogram modification block, median filter block and Sobel edge sharping block.The key algorithms are programmed with VHDL hardware programming language. And this paper introduces the implementation of each modul in detail. In addition, the algorithms are executed in the software QuartusII. The results of testing demonstrate that the design has achieved the needs of high speed and can be used in other fields.
Keywords/Search Tags:Histogram modification, Median filter, Edge sharping, FPGA, VHDL
PDF Full Text Request
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