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Implementation Of Video Capture Output System Based On FPGA

Posted on:2012-01-07Degree:MasterType:Thesis
Country:ChinaCandidate:H J ZhangFull Text:PDF
GTID:2178330335955587Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
With the development of information technology, digital image processing technology is widely used in telecommunications, remote sensing, security, medicine, video surveillance, industrial production, commerce and many other fields. In practice, previously we can choose DSP (Digital Signal Processor) and ARM (Advanced RISC Machines) as image processing chip. In recent years, the central processing unit (CPU) and digital processor core (DSP) have been integrated in a new generation of FPGA, soft/hard collaborative design can be realized in one FPGA, it provides a powerful hardware support of programmable system and makes the FPGA digital image processing technology a very broad development prospects in the future.This paper starts from the basic theory of video processing, firstly the paper compares the current video processing chip, selects one FPGA chip for image processing, and then introduces the basic process of video acquisition and processing on FPGA platform, including image acquisition, storage, processing and display of the four parts. Using the virtex-II Pro FPGA board, the system has accomplished a reconfigurable platform for image processing algorithm. Then it designs a 12C-config module which can configure the ADC chip Tvp5150 properly and introduces detail information on the part of the video signal format conversion, including ITUR656 video decoding, video interpolation, de-interleaving, and color space conversion. The part of the image cache storage chooses the ping-pong mode and uses two SRAM to achieving. Finally, the system selects the VGA monitor to display video. In order to accomplish the video signal conversion and processing, the entire process chooses the Verilog HDL hardware description language to realizing the video signal conversion and processing. In the image processing module, the system selects the median filter and edge detection algorithm to process the graph. The sampling frequency of System is 27MHZ, frame size is 640×480, color depth is 24bit, frame rate up to 25.The whole design module is simulated with software Xinlix ISE and Modelsim. The simulation results meet the design requirements, and it gives the results of the analysis.
Keywords/Search Tags:Image Processing, FPGA, Median Filter, Edge Detection
PDF Full Text Request
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